Integrated circuits that can be customised may be classified into one of two broad classes: programmable and non-programmable. Programmable devices, such as Field-Programmable Gate Arrays (FPGAs), are semiconductor integrated circuit devices that can be programmed once or repeatedly reprogrammed to perform functions customised to particular applications. Non-programmable customised devices, such as application-specific integrated circuits (ASICs), also perform functions customised to particular applications but customisation occurs through a manufacturing-based process. Once an ASIC has been manufactured, these functions are fixed and cannot be altered. Also available are integrated circuits that incorporate both programmable and non-programmable circuitry in a single device.
The ability to easily program and reprogram FPGAs makes them well suited for developing new integrated circuits. However, FPGAs typically occupy between 20 and 40 times the surface area of semiconductor or footprint than an equivalent standard-cell ASIC, have poorer power and circuit speed performance, offer fewer degrees of freedom for user customisation, provide a smaller number of gates available for implementation, and are also considerably more expensive on a per-unit basis. Moreover, once a new circuit has been verified to function properly, programmability is normally no longer required. At this point, it is more important to have a low cost device such as an ASIC. However, the cost of initially developing a new customised ASIC is extremely high, and such non-recurring engineering (NRE) costs make ASICs attractive only when produced in high volumes so that the NRE costs can be absorbed without appreciably increasing the cost per unit, or when the number of gates required exceeds the capacity of an FPGA, or when specialised functionality not available in an FPGA is required, or when high speed or low power operation is required and cannot be achieved with an FPGA.
To alleviate the high development costs of a new ASIC, an FPGA can be used to develop a prototype of a new integrated circuit which, once verified, can then be translated into an equivalent ASIC circuit. However, the translation process is not straightforward and can be excessively time consuming and costly. Moreover, structural differences between FPGA and ASIC circuit components and interconnects can cause the FPGA and ASIC implementations of the final circuit to behave differently, which greatly complicates the translation process. Further, as FPGAs are unable to provide as many gates as ASICs, such an approach necessarily limits the number of gates that can be so prototyped. A possible workaround is to use multiple FPGAs for prototyping and a single ASIC for production; however, this even further complicates the translation process. Moreover, multiple FPGAs in a prototype system cannot be readily substituted with an ASIC due to the difference in form factor of their respective packages.
To address these difficulties, a customisable integrated circuit platform referred to as a ‘structured ASIC’ (sometimes referred to as a ‘platform ASIC’) has been developed. Structured ASICs provide a compromise between the low-cost reprogrammability of FPGAs and the low per-unit cost of ASICs. A structured ASIC provides a variety of predefined generic active circuit blocks or modules, including input/output (I/O) blocks, diffused memory, diffused intellectual property (commonly referred to as ‘diffused IP’; i.e., predefined complex custom circuit elements such as phase-locked loops (PLLs), microprocessors, etc), and logic fabric (which may include look-up-tables (LUTs), programmable arrays or alternately a ‘sea of gates’ or some other form of logic fabric), which for convenience are all referred to herein as logic blocks or logic components.
A structured ASIC is physically customised by defining only the fixed routing layers and/or vias that interconnect these logic blocks to define a new circuit topology. (Some structured ASICs can also be effectively “customized” through the use of programmable lookup tables which reside in the logic fabric; however, the physical implementation of the lookup tables is fixed and cannot be altered.) Thus the predefined logic blocks provide the benefits of low unit cost and efficient use of semiconductor real estate, while the routing layers provide an ability to customise at a relatively low cost, since NRE costs associated with predefined layers can be amortised across many customers and/or products. In particular, the ability to develop prototypes using the same ASIC logic blocks that will be used in the final product avoids the need to translate the prototype circuit from an FPGA platform to the ASIC platform. However, despite the many advantages of structured ASIC technology, the development of new prototype circuits nevertheless requires one or more new routing layer and/or via masks to be developed, and this can be time consuming, prone to error, and expensive. Maskless technologies that use e-beam or other approaches to customise the routing have been developed as an alternative, but are an expensive and time consuming method of customising interconnect compared to traditional FPGAs.
One of the advantages of FPGAs over ASICs is that reprogrammability can be used to facilitate circuit design debugging. If a particular node internal to the FPGA needs to be observed, a debugging version of the circuit can be programmed to connect that node to an otherwise unused input/output pin, or alternately to provide an external input signal to a portion of the circuit that would not normally be accessible in the final implementation. Additionally, this allows the circuit to be developed in stages, and tested and debugged incrementally, which can greatly simplify circuit design verification. Further, if required, special purpose test circuits can be incorporated in the circuit during testing, provided that a sufficient number of gates is available to accommodate these test circuits, and then discarded if desired for a production version of the circuit. None of these techniques are readily available in the case of ASICs due to the high cost and manufacturing time associated with ASIC prototype production. Due to the potentially larger size and complexity of ASICs and the lack of availability of the above techniques, ASICs are consequently much more difficult to debug than FPGAs.
Since ASICs lack reprogrammability, the traditional ASIC approach typically requires compromises to be made in providing the physical die resources necessary to ensure that a device can be tested and debugged sufficiently to verify the correctness of the design. (The word ‘die’ is a term of art that refers to a portion of a processed semiconductor wafer that provides an electronic, optoelectronic, or other type of device. In general, a semiconductor wafer is processed to produce a large number of typically identical devices in order to take advantage of the economies of scale available from batch processing. After these devices are formed in the wafer, the processed wafer is cut into a large number of typically identical rectangular or square pieces, each piece subsequently being packaged to provide a single saleable unit. Each of those pieces of the wafer is referred to as a die or chip.)
There are typically two classes of testing that need to be performed on a given circuit design, respectively referred to herein as “design verification” and “production test”. It is a general requirement that an integrated circuit be testable in order to verify the circuit, a process referred to as design verification. However, additional test measures are usually implemented to ensure that production quality can be monitored to eliminate defective parts as they are manufactured, a process referred to herein as “production test”. Once the circuit design has been verified, there is usually no further need to repeat that verification.
The ability to test a selected logic circuit under specified conditions is limited by the degree to which the state of logic input nodes can be manipulated (referred to as “controllability”) and the ability to monitor the state of logic output nodes (referred to as “observability”). Non-binary (i.e., analog) circuits are also subject to the same principles.
Typically, dedicated test structures such as ‘boundary scan’ or internal scan paths are added to the circuit topology to facilitate at least production test. Production test observability and controllability is generally achieved by configuring the logic circuits internally into dedicated test configurations during which the device is otherwise non-operational.
In order to provide the necessary observability and controllability for design verification of an ASIC, various methods can be employed. Usually, the external input and output pins are controlled and observed respectively by means external to the device. The means of control and observation can be provided by either application-specific test hardware, or general purpose test equipment configured to suit design verification of the device under test. However, the approach whereby external input and output pins provide the means of testing the device is necessarily limited by the degree of controllability and observability that the external pins are able to provide. Further difficulty often exists in providing the necessary capability in the external means of control and observation to provide the degree of control and observation required to perform design verification. This is due to the speed and complexity of the necessary device stimuli and response behaviour, hence the provision of external means of control and observation having the desired degree of complexity and performance is usually complex and expensive.
To overcome the limitations of design verification by external stimulation and observation, alternately or additionally certain circuit functionality internal to the device itself can be employed to enhance controllability and observability and therefore device testability. This internal circuit functionality can be either be naturally included in the circuit design as part of its normal functioning, or incorporated specifically and additionally for the purpose of enhancing testability, and frequently is provided as a combination of naturally included functionality and specific additional functionality. Incorporation of specific additional functionality can be useful for enhancing testability, but requires the addition of logic components specifically for the purposes of design verification into the device. The addition of test-specific logic components for testability necessarily imposes an overhead on both the design process and device manufacture because such components are designed prior to device fabrication, require additional semiconductor die area, and themselves need to be verified and tested as with the other circuitry of the device.
The state of the art in integrated circuit production is constantly evolving with such devices becoming more complex, operating at higher speeds, and incorporating an increasing amount of circuitry in a single device. Such trends place increasing demands on testability due to the various controllability and observability limitations of the approaches to test described above. The addition of internal connectivity and test-specific logic functionality to ASICs is a useful approach for enhancing testability, but is wasteful of semiconductor die area and introduces unwanted complexity into the design process.
Structured ASICs have similar debugging issues to those described above for ASICs. Unlike an FPGA, structured ASICs go through a physical manufacturing process in order to be “customised”. This manufacturing process is costly and does not provide the quick turn-around time that is required to match the debugging capabilities of FPGAs.
In summary, while FPGAs offer rapid prototyping turnaround, low NRE costs, eliminate some design complexity (e.g. clock distribution), and permit easier debugging because they are reprogrammable, compared to ASICs they are expensive, slow, offer lower gate counts, consume more power, and provide fewer degrees of design freedom. Compared to FPGAs, ASICs are larger (more integrated), provide higher performance and lower power consumption, and are more malleable and much cheaper to manufacture in volume. However, they are also more complex and expensive to design, very expensive and slow to prototype, require detailed consideration of more factors (e.g., clock distribution), and are more difficult to debug. Structured ASICs attempt to provide a compromise between ASICs and FPGAs; however they still lack the reprogrammability that makes FPGAs attractive: the capability to be entirely reprogrammed without going through a physical manufacturing process. Another significant disadvantage of structured ASICs compared to FPGAs is that because they must go through a physical manufacturing process in order to be customized or “programmed” for use, they cannot be offered to customers as a standard component. A given FPGA can serve multiple customers and various end uses; in contrast, after manufacturing is complete, a given structured ASIC is specific to an individual customer and specific end use. It is desired to provide a reprogrammable integrated circuit, an interconnect die, a logic die, a reprogrammable interconnect, and an integrated circuit production process that alleviate one or more of the above difficulties, or at least provide a useful alternative.